ICC Parameter Average supply current for ALU operation tCLK = min, (1 MCLK cycle) Average standby current tCLK =  Average supply current for DRAM operation ACP tCLK = min, (4 MCLK cycles) Average supply current for DRAM operation PRE tCLK = min, (4 MCLK cycles) Average supply current for DRAM operation DUP tCLK = min, (8 MCLK cycles) Average supply current for DRAM operation RDB tCLK = min, (2 or 3 MCLK cycles) Average supply current for DRAM operation UWB tCLK = min, (2 or 3 MCLK cycles) Average supply current for DRAM operation VDX tCLK = min, (4 MCLK cycles) Average supply current for video output tVCLK = min -10A, -10 260 20 105 55 55 160 160 80 70 -12 215 20 85 40 40 130 130 60 70 Unit mA mA mA mA mA mA mA mA mA
7 Electrical Specifications
ICC ICC ICC ICC
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Rev. 1.03 3D-RAM (M5M410092B)
measurement levels illustrated in Figures 7.3 through 7.6. Pixel ALU Timing Parameters The timing parameters of M5M410092B-10 and -12 are presented in Table 7.4.
AC Specifications
Every AC timing parameter is illustrated in at least one of the timing figures in Chapter 8. The "Refer" column in each timing table refers to the exact
Table 7.4
Pixel ALU timing parameters M5M410092B -10A -10 Min 10 T 4 4 0 40 3 1.5 3 1.5 3 1.5 3 Max 16000 -- -- -- -- -- -- -- -- -- -- -- Min 12 5 5 0 48 4 1.5 4 1.5 4 1.5 4 -12 Max 16000 -- -- -- -- -- -- -- -- -- -- -- Unit Refer ns ns ns ns ns ns ns ns ns ns ns ns t1 t2 t3 t6 t7 t8 t9 t8 t9 t8 t9 t8 Ch. 8 Figure 4 4 4 1 2 4 4 4 4 4 4 5
Symbol Parameter tCLK tCLKH tCLKL tRSS tRSP tENS tENH tOPS tOPH tADS tADH tDQS Master clock MCLK cycle time MCLK high pulse width MCLK low pulse width RESET setup time RESET pulse width PALU_EN setup time PALU_EN hold time PALU_OP setup time PALU_OP hold time PALU_A setup time PALU_A hold time PALU_DQ, PALU_DX setup time PALU_DQ, PALU_DX hold time PALU_WE setup time PALU_WE hold time
Min 10 4 4 0 40 3 1.5 3 1.5 3 1.5 3
Max 16000 -- -- -- -- -- -- -- -- -- -- --
tDQH
1.5
--
1.5
--
1.5
--
ns
t9
5
tWES tWEH
T
3 1.5
-- --
3 1.5
-- --
4 1.5
-- --
ns ns
t8 t9
4 4
tCLK = 10.0 ns except that for the alpha saturate logic tCLK = 12.0 ns.
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7 Electrical Specifications
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Rev. 1.03 3D-RAM (M5M410092B)
Table 7.4 Pixel ALU timing parameters (con't.) M5M410092B -10A Symbol Parameter tBES tBEH tCLZ PALU_BE setup time PALU_BE hold time MCLK to PALU_DQ low impedance PALU_DQ access time PALU_DQ data valid time MCLK to PALU_DQ high impedance PASS_IN setup time PASS_IN hold time MCLK to valid PASS_OUT PASS_OUT data valid time MCLK to valid HIT Min 3 1.5 4 Max -- -- -- Min 3 1.5 4 -10 Max -- -- -- Min 4 1.5 5 -12 Max -- -- -- Unit Refer ns ns ns t8 t9 t10 Ch. 8 Figure 4 4 4
tCQ
-- 4 --
14 -- 4
-- 4 --
14 -- 4
-- 4 --
18 -- 4
ns ns ns
t11 t12 t13
4 4 4
7 Electrical Specifications
tCVD tCHZ
tPSS tPSH tCPS tCPSV tCHT
2 0 -- 3 --
-- -- 6 -- 35
2 0 -- 3 --
-- -- 6 -- 35
3 0 -- 3 --
-- -- 8 -- 35
ns ns ns ns ns
t8 t9 t11 t12 t11
5 5 5 5 6
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Rev. 1.03 3D-RAM (M5M410092B)
edge of the first operation to the MCLK rising edge of the second operation. Both MCLK edges are measured at 1.5 V.
DRAM Timing Parameters The measurements of the DRAM interlock timings in Tables 7.6 and 7.7 are from the MCLK rising Table 7.5
Minimum requirements of the DRAM timing parameters M5M410092B Ch. 8 Figure -- 7 7 7 7
Symbol tREF tDENS tDENH tDOPS tDOPH tDBKS tDBKH tDADS tDADH
Parameter Refresh interval for array DRAM_EN setup time DRAM_EN hold time DRAM_OP setup time DRAM_OP hold time DRAM_BS setup time DRAM_BS hold time DRAM_A setup time DRAM_A hold time
-10A, -10 17 3 1.5 3 1.5 3 1.5 3 1.5
-12 17 4 1.5 4 1.5 4 1.5 4 1.5
Unit Refer ms ns ns ns ns ns ns ns ns -- t8 t9 t8 t9 t8 t9 t8 t9
7 7 7
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7 Electrical Specifications
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ELECTRONIC DEVICE GROUP
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Rev. 1.03 3D-RAM (M5M410092B)
Table 7.6
Minimum requirements of the DRAM interlock timings for operations on same bank M5M410092B Ch. 8 Timing Figure 7 7 8 9 7 7 8 10 7 10 8 9 8 9 10 9 9 9
Symbol tdABS tdAPS
a
Parameter Access Page to Block Transfer Access Page to Precharge Bank Access Page to Duplicate Page Access Page to Video Transfer Block Transfer to Block Transfer Block Transfer to Precharge Bank Block Transfer to Duplicate Page Block Transfer to Video Transfer Precharge Bank to Access Page Precharge Bank to Precharge Bank Duplicate Page to Block Transfer Duplicate Page to Precharge Bank Duplicate Page to Duplicate Page Duplicate Page to Video Transfer Video Transfer to Block Transfer Video Transfer to Precharge Bank Video Transfer to Duplicate Page Video Transfer to Video Transfer
-10A, -10 36 60 48 40 20 20 20 20 40 10 80 80 80 80 40 20 40 80
-12 36 72 48 48 24 24 24 24 48 12 96 96 96 96 48 24 48 96
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tdADS tdAVS tdBBS tdBPS tdBDS tdBVS
b
7 Electrical Specifications
tdPAS
tdPPS tdDBS tdDPS tdDDS tdDVS tdVBS tdVPS tdVDS tdVVS
a. The maximum timing limit from ACP to PRE is 100,000 ns. b. The operation from PRE to ACP requires at least two clock cycles. At the first clock rising edge, PRE starts. At the second clock rising edge, the preparation for ACP starts.
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M5M410092B Symbol tdAAD tdABD tdAPD tdADD tdAVD tdBAD tdBBD tdBPD tdBDD tdBVD tdPAD tdPBD tdPPD tdPDD tdPVD tdDAD tdDBD tdDPD tdDDD tdDVD tdVAD tdVBD tdVPD tdVDD tdVVD Parameter Access Page to Access Page Access Page to Block Transfer Access Page to Precharge Bank Access Page to Duplicate Page Access Page to Video Transfer Block Transfer to Access Page Block Transfer to Block Transfer Block Transfer to Precharge Bank Block Transfer to Duplicate Page Block Transfer to Video Transfer Precharge Bank to Access Page Precharge Bank to Block Transfer Precharge Bank to Precharge Bank Precharge Bank to Duplicate Page Precharge Bank to Video Transfer Duplicate Page to Access Page Duplicate Page to Block Transfer Duplicate Page to Precharge Bank Duplicate Page to Duplicate Page Duplicate Page to Video Transfer Video Transfer to Access Page Video Transfer to Block Transfer Video Transfer to Precharge Bank Video Transfer to Duplicate Page Video Transfer to Video Transfer -10A, -10 40 10 40 40 40 10 20 10 10 10 10 10 10 10 10 80 10 40 80 80 40 10 20 40 80 -12 48 12 48 48 48 12 24 12 12 12 12 12 12 12 12 96 12 48 96 96 48 12 24 48 96 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Ch. 8 Timing Figure 11 11 11 12 13 11 11 11 11 13 11 11 11 11 13 12 12 12 12 13 13 13 13 13 13
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7 Electrical Specifications
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Rev. 1.03 3D-RAM (M5M410092B)
Video Buffer Timing Parameters Table 7.7 Video Buffer timing parameters M5M410092B -10A, -10 Symbol tVCLK tVCLKH tVCLKL tVCES tVCEH tVQ Parameter VID_CLK cycle time VID_CLK high pulse width VID_CLK low pulse width VID_CKE setup time VID_CKE hold time VID_Q access time from VID_CLK VID_Q valid after VID_CLK VID_Q output low impedance VID_Q output high impedance VID_Q access time from VID_OE high VID_Q valid after VID_OE low Initial VDX after last internal VID_CLK Initial VDX VID_CLK before next internal Min 12 5 5 4 0 -- 3 3 -- -- -- 14 80 -- -- 20 60 Max -- -- -- -- -- 8 -- -- 3 9 -- -- -- 80 25 -- -- Ch. 8 Min Max Unit Refer Figure 12 5 5 4 0 -- 3 3 -- -- -- 14 80 -- -- 20 60 -- -- -- -- -- 8 -- -- 3 9 -- -- -- 80 25 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t1 t2 t3 t8 t9 t11 t12 t16 t15 t17 t14 -- -- t11 t11 -- -- 14 14 14 14 14 14 14 14 14 14 14 15 15 15 16 16 16 -12
7 Electrical Specifications
tVQVC tVLZ tVHZ tVQE tVQVE tVXCI1 tVXCI2 tVXQFI tQSF tVXC1 tVXC2
VID_QSF delay time after initial VDX VID_QSF delay time from internal VID_CLK 38 Normal VDX after internal VID_CLK 38 Normal VDX VID_CLK 38 before next internal
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Boundary-Scan Timing Parameters Table 7.8 Boundary-Scan timing parameters M5M410092B -10A, -10, -12 Symbol tSCLK tSCLKH tSCLKL tSCNTS tSCNTH tSCNIS tSCNIH tSLZ tSQ tSVD tSHZ tSCNRS tSCNRP Parameter SCAN_TCK cycle time SCAN_TCK high pulse width SCAN_TCK low pulse width SCAN_TMS setup time SCAN_TMS hold time SCAN_TDI setup time SCAN_TDI hold time SCAN_TCK to SCAN_TDO low impedance SCAN_TDO access time SCAN_TDO data valid time SCAN_TCK to SCAN_TDO high impedance SCAN_RST setup time SCAN_RST pulse width Min 100 40 40 8 26 8 26 -- -- 8 -- 8 30 Max -- -- -- -- -- -- -- 20 26 -- 20 -- -- Unit Refer ns ns ns ns ns ns ns ns ns ns ns ns ns t1 t2 t3 t8 t9 t8 t9 t18 t19 t20 t21 t6 t7
Ch. 8 Figure 17 17 17 17 17 17
17 17 17 17 18 18
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7 Electrical Specifications
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Rev. 1.03 3D-RAM (M5M410092B)
7 Electrical Specifications
116
8
Timing Diagrams
ELECTRONIC DEVICE GROUP
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Rev. 1.03 3D-RAM (M5M410092B)
Timing Diagrams
This chapter shows 18 timing diagrams, which are summarized in Table 8.1. These diagrams show the gross timing specifications. Refer to Chapter 7 for exact timing measurements. Also, the entries of parameter values from Tables 7.4 through 7.9 are repeated here for convenient reference.
Table 8.1 Timing diagram figures Figure
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 Power on reset Restart reset DRAM array initialization Pixel port read Pixel port write Pick logic timing DRAM operations on the same bank (1) DRAM operations on the same bank (2) DRAM operations on the same bank (3)
Description
DRAM operations between two different banks (1) DRAM operations between two different banks (2) DRAM operations between two different banks (3) Internal VID_CLK and video output timing Video output sequence from initial VDX for normal and reversed modes Continuous video output sequence in normal mode during display Boundary scan Boundary scan reset
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8 Timing Diagrams
DRAM operations on the same bank (4)
ELECTRONIC DEVICE GROUP
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Rev. 1.03 3D-RAM (M5M410092B)
VDD > 500s MCLK > 9 cycles
RESET tRSS Internal Function Stabilize internal power supply Reset Registers Initialize DRAM Array Start Normal Operation
M1020
Figure 8.1 Power on reset
> 9 cycles MCLK tRSP RESET tRSS Internal Function tRSS Reset Registers Initialize DRAM Array Start Normal Operation
8 Timing Diagrams
M1021
Figure 8.2 Restart reset
Table 8.2 Reset timing parameters M5M410092B Symbol tRSS tRSP Parameter RESET setup time RESET pulse width -10A, -10 Min 0 40 Max -- -- Min 0 48 -12 Max -- -- ns ns t6 t7 Unit Refer
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Rev. 1.03 3D-RAM (M5M410092B)
MCLK
DRAM_OP
ACP
ACP
ACP
ACP
PRE
PRE
PRE
PRE
DRAM_BS Internal Function
A
B
C
D Initialize DRAM Array
A
B
C
D Start Normal Operation
OR
MCLK
DRAM_OP
ACP
PRE
ACP
PRE
ACP
PRE
ACP
PRE
DRAM_BS Internal Function
A
A
B
B
C
C
D
D Start Normal Operation
Initialize DRAM Array
M1019
Figure 8.3 DRAM array initialization
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8 Timing Diagrams
ELECTRONIC DEVICE GROUP
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Rev. 1.03 3D-RAM (M5M410092B)
tCLK MCLK tENS PALU_EN tOPS PALU_OP tWES PALU_WE tADS PALU_A tBES PALU_BEn
tCLKH tCLKL
tENH
tOPH 111 tWEH 000
tADH 000111 tBEH Block : Word
PALU_DQ[8n+7..8n] tCLZ tCQ
Valid ID tCVD tCHZ tCQ
Valid Data
M1018
Note: Refer to Figure 2.6 for an example of combined operations of Pixel ALU read and write.
8 Timing Diagrams
Figure 8.4 Pixel port read
MCLK
1
2
3
4
5
6
7
8
9
10
PALU_EN
PALU_OP
111
100
101
010 or 011
000 or 001
PALU_WE
PALU_A
Register
Block:xxx
Block:xxx
Block:Word
PALU_BEn tDQS PALU_DQ[8n+7..n] Reg Data tDQH Dirty Tag Dirty Tag New Data New Data
PALU_DXn
Reg Data
New Data
New Data tPSS tPSH
Pass_In
PASS_IN
PASS_OUT tCPS tCPSV
M1017
Figure 8.5
Pixel port write
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Rev. 1.03 3D-RAM (M5M410092B)
Table 8.3 Pixel ALU timing parameters M5M410092B Symbol tCLK tCLKH tCLKL tENS tENH tOPS tOPH tADS tADH tWES tWEH tBES tBEH tCLZ tCQ tCVD tCHZ tDQS tDQH tPSS tPSH tCPS tCPSV
T
Parameter Master clock MCLK cycle time MCLK high pulse width MCLK low pulse width PALU_EN setup time PALU_EN hold time PALU_OP setup time PALU_OP hold time PALU_A setup time PALU_A hold time PALU_WE setup time PALU_WE hold time PALU_BE setup time PALU_BE hold time MCLK to PALU_DQ low impedance PALU_DQ access time PALU_DQ data valid time MCLK to PALU_DQ high impedance PALU_DQ, PALU_DX setup time PALU_DQ, PALU_DX hold time PASS_IN setup time PASS_IN hold time MCLK to valid PASS_OUT PASS_OUT data valid time 10 4 4 3 1.5 3 1.5 3 1.5 3 1.5 3 1.5 4 -- 4 -- 3 1.5 2 1.5 -- 3
-10A Min Max Min
-10 Max Min 12 5 5 4 1.5 4 1.5 4 1.5 4 1.5 4 1.5 5 -- 4 -- 4 1.5 3 1.5 -- 3
-12 Max 16000 -- -- -- -- -- -- -- -- -- -- -- -- -- 18 -- 4 -- -- -- -- 8 --
Unit Refer ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t1 t2 t3 t8 t9 t8 t9 t8 t9 t8 t9
16000 10 T 16000 -- -- -- -- -- -- -- -- -- -- -- -- -- 14 -- 4 -- -- -- -- 6 -- 4 4 3 1.5 3 1.5 3 1.5 3 1.5 3 1.5 4 -- 4 -- 3 1.5 2 1.5 -- 3 -- -- -- -- -- -- -- -- -- -- -- -- -- 14 -- 4 -- -- -- -- 6 --
t9 t10 t11 t12 t13 t8 t9 t8 t9 t11 t12
tCLK = 10.0 ns except that for the alpha saturate logic tCLK = 12.0 ns.
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8 Timing Diagrams
t8
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Rev. 1.03 3D-RAM (M5M410092B)
MCLK
1
2
3
4
5
6
7
8
9
10
PALU_EN
PALU_OP
111
011
PALU_WE
PALU_A
000101
Block:Word
PALU_BE[2..0]
PALU_BE3
PALU_DQ[31..0]
XEXXXXXX
Data
PASS_IN
PASS_OUT Note 1 HIT tCHT tCHT Note 2
8 Timing Diagrams
M1016
Note: 1. The HIT signal is cleared by writing to the Compare Control register. 2. The HIT signal can be set by the comparison result from the PASS_IN and PASS_OUT pins, which are generated two cycles before the HIT signal is.
Figure 8.6 Picking Logic timing
Table 8.4 Picking Logic timing parameter M5M410092B Symbol tCHT Parameter MCLK to valid HIT -10A, -10 Min -- Max 35 Min -- -12 Max 35 ns t11 Unit Refer
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8 Timing Diagrams
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ELECTRONIC DEVICE GROUP
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Rev. 1.03 3D-RAM (M5M410092B)
tdPAS
tdABS
tdBBS
tdBPS
MCLK
tDENS tDENH
DRAM_EN
tDOPS tDOPH
DRAM_OP
tDBKS
PRE
NOP
tDBKH
ACP
NOP
BKX
NOP
BKX
NOP
PRE
DRAM_BS
tDADS
A
tDADH
A
A
A
A
DRAM_A
PAGE
PAGE
BLOCK
BLOCK
PAGE
M1015
tdAPS
MCLK
DRAM_EN
DRAM_OP
PRE
NOP
ACP
NOP
BKX
NOP
BKX
NOP
PRE
DRAM_BS
A
A
A
A
A
8 Timing Diagrams
DRAM_A
PAGE
PAGE
BLOCK
BLOCK
PAGE
M1043
Note: BKX means any block transfer operation, such as UWB, MWB, or RDB.
Figure 8.7 DRAM operations on the same bank (1)
tdADS
tdDDS
tdDBS
tdBDS
MCLK
DRAM_EN
DRAM_OP
ACP
NOP
DUP
NOP
DUP
NOP
BKX
NOP
DUP
DRAM_BS
A
A
A
A
A
DRAM_A
PAGE
PAGE
PAGE
BLOCK
PAGE
M1014
Note: BKX means any block transfer operation, such as UWB, MWB, or RDB.
Figure 8.8 DRAM operations on the same bank (2)
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Table 8.5 Minimum requiremens of the DRAM port interface timing parameters Symbol tDENS tDENH tDOPS tDOPH tDBKS tDBKH tDADS tDADH Parameter DRAM_EN setup time DRAM_EN hold time DRAM_OP setup time DRAM_OP hold time DRAM_BS setup time DRAM_BS hold time DRAM_A setup time DRAM_A hold time M5M410092B -10A, -10 3 1.5 3 1.5 3 1.5 3 1.5 -12 4 1.5 4 1.5 4 1.5 4 1.5 ns ns ns ns ns ns ns ns t8 t9 t8 t9 t8 t9 t8 t9 Unit Refer Timing Figure 8.7 8.7 8.7 8.7 8.7 8.7 8.7 8.7
Table 8.6 Minimum requirements of the DRAM interlock timings for operations on same bank Symbol tdABS tdAPSa tdADS tdBBS tdBPS tdBDS tdPAS
b
Parameter Access Page to Block Transfer Access Page to Precharge Bank Access Page to Duplicate Page Block Transfer to Block Transfer Block Transfer to Precharge Bank Block Transfer to Duplicate Page Precharge Bank to Access Page Duplicate Page to Block Transfer Duplicate Page to Duplicate Page
M5M410092B -10A, -10 36 60 48 20 20 20 40 80 80 -12 36 72 48 24 24 24 48 96 96
Unit ns ns ns ns ns ns ns ns ns
Timing Figure 8.7 8.7 8.8 8.7 8.7 8.8 8.7 8.8 8.8
tdDBS tdDDS
a. The maximum timing limit from ACP to PRE is 100,000 ns. b. The operation from PRE to ACP requires at least two clock cycles. At the first clock rising edge, PRE starts. At the second clock rising edge, the preparation for ACP starts.
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8 Timing Diagrams
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Rev. 1.03 3D-RAM (M5M410092B)
tdAVS
tdVDS
tdDVS
tdVPS
MCLK
DRAM_EN
DRAM_OP
ACP
NOP
VDX
NOP
DUP
VDX
NOP
PRE
DRAM_BS
A
A
A
A
A
DRAM_A
PAGE
LINE
PAGE
LINE
PAGE
M1013
tdDPS tdVVS
MCLK
DRAM_EN
DRAM_OP
ACP
NOP
VDX
NOP
DUP
VDX
NOP
PRE
DRAM_BS
A
A
A
A
A
8 Timing Diagrams
DRAM_A
PAGE
LINE
PAGE
LINE
PAGE
M1044
Figure 8.9 DRAM operations on the same bank (3)
tdVBS
tdBVS
tdPPS
MCLK
DRAM_EN
DRAM_OP
VDX
NOP
BKX
NOP
VDX
NOP
PRE
NOP
PRE
DRAM_BS
A
A
A
A
A
DRAM_A
LINE
BLOCK
LINE
PAGE
PAGE
M1012
Note: BKX means any block transfer operation, such as UWB, MWB, or RDB.
Figure 8.10 DRAM operations on the same bank (4)
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Rev. 1.03 3D-RAM (M5M410092B)
Table 8.7 Minimum requirements of the DRAM interlock timings for operations on same bank Symbol Parameter M5M410092B -10A, -10 tdAVS tdBVS tdPPS tdDPS tdDVS tdVBS tdVPS tdVDS tdVVS Access Page to Video Transfer Block Transfer to Video Transfer Precharge Bank to Precharge Bank Duplicate Page to Precharge Bank Duplicate Page to Video Transfer Video Transfer to Block Transfer Video Transfer to Precharge Bank Video Transfer to Duplicate Page Video Transfer to Video Transfer 40 20 10 80 80 40 20 40 80 -12 48 24 12 96 96 48 24 48 96 ns ns ns ns ns ns ns ns ns Unit Timing Figure 8.9 8.10 8.10 8.9 8.9 8.10 8.9 8.9 8.9
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8 Timing Diagrams
ELECTRONIC DEVICE GROUP
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Rev. 1.03 3D-RAM (M5M410092B)
tdBBD tdPPD tdPAD tdABD tdBAD tdBPD tdPDD
MCLK
DRAM_EN
DRAM_OP
PRE
PRE
ACP
BKX
NOP
ACP
BKX
PRE
DUP
DRAM_BS
A
B
C
D
B
C
D
B
DRAM_A
PAGE
PAGE
PAGE
BLOCK
PAGE
BLOCK
PAGE
PAGE
M1011
tdAAD tdPBD
tdAPD tdBDD
MCLK
DRAM_EN
DRAM_OP
PRE
PRE
ACP
BKX
NOP
ACP
BKX
PRE
DUP
DRAM_BS
A
B
C
D
B
C
D
B
8 Timing Diagrams
DRAM_A
PAGE
PAGE
PAGE
BLOCK
PAGE
BLOCK
PAGE
PAGE
M1045
Note: BKX means any block transfer operation, such as UWB, MWB, or RDB.
Figure 8.11 DRAM operations between two different banks (1)
tdDDD tdADD tdDBD tdDPD
tdDAD
MCLK
DRAM_EN
DRAM_OP
ACP
DUP
BKX
DUP
PRE
ACP
DRAM_BS
A
B
A
C
A
D
DRAM_A
PAGE
PAGE
BLOCK
PAGE
PAGE
PAGE
M1010
Figure 8.12 DRAM operations between two different banks (2)
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Rev. 1.03 3D-RAM (M5M410092B)
Table 8.8 Minimum requirement of the DRAM interlock timings for operations between two different banks Symbol Parameter M5M410092B -10A, -10 tdAAD tdABD tdAPD tdADD tdBAD tdBBD tdBPD tdBDD tdPAD tdPBD tdPPD tdPDD tdDAD tdDBD tdDPD tdDDD Access Page to Access Page Access Page to Block Transfer Access Page to Precharge Bank Access Page to Duplicate Page Block Transfer to Access Page Block Transfer to Block Transfer Block Transfer to Precharge Bank Block Transfer to Duplicate Page Precharge Bank to Access Page Precharge Bank to Block Transfer Precharge Bank to Precharge Bank Precharge Bank to Duplicate Page Duplicate Page to Access Page Duplicate Page to Block Transfer Duplicate Page to Precharge Bank Duplicate Page to Duplicate Page 40 10 40 40 10 20 10 10 10 10 10 10 80 10 40 80 -12 48 12 48 48 12 24 12 12 12 12 12 12 96 12 48 96 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Timing Figure 8.11 8.11 8.11 8.12 8.11 8.11 8.11 8.11 8.11 8.11 8.11 8.11 8.12 8.12 8.12 8.12
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8 Timing Diagrams
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Rev. 1.03 3D-RAM (M5M410092B)
tdVVD tdDVD tdBVD tdVBD tdVPD tdPVD tdVAD tdVDD tdAVD
MCLK
DRAM_EN
DRAM_OP
DUP
BKX
VDX
BKX
PRE
VDX
ACP
DUP
NOP
VDX
DRAM_BS
A
B
C
B
D
B
D
A
C
DRAM_A
PAGE
BLOCK
LINE
BLOCK
PAGE
LINE
PAGE
PAGE
LINE
M1009
Figure 8.13 DRAM operations between two different banks (3)
Table 8.9 Minimum requirement of the DRAM interlock timings for operations between two different banks Symbol Parameter M5M410092B -10A, -10 -12 48 12 12 96 48 12 24 48 96 ns ns ns ns ns ns ns ns ns Unit
8 Timing Diagrams
tdAVD tdBVD tdPVD tdDVD tdVAD tdVBD tdVPD tdVDD tdVVD
Access Page to Video Transfer Block Transfer to Video Transfer Precharge Bank to Video Transfer Duplicate Page to Video Transfer Video Transfer to Access Page Video Transfer to Block Transfer Video Transfer to Precharge Bank Video Transfer to Duplicate Page Video Transfer to Video Transfer
40 10 10 80 40 10 20 40 80
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8 Timing Diagrams
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ELECTRONIC DEVICE GROUP
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Rev. 1.03 3D-RAM (M5M410092B)
tVCLKH tVCLKL tVCLK
VID_CLK
tVCES
1 tVCEH
1
VID_CKE Internal VID_CLK
VID_OE
tVLZ
VID_Q
tVQVC
Data 1
tVQ
Data 2
tVQVE tVHZ tVQE
Data 2
Data 3
Data 4
Data 5
Data 6
M1006
Note: 1. The deassertion of VID_CKE at the current VID_CLK rising edge will mask out the next internal VID_CLK cycle. 2. Timings are measured from the VID_CLK pin or from the VID_OE pin.
Figure 8.14 Internal VID_CLK and video output timing
MCLK
8 Timing Diagrams
DRAM_OP
VDX
DRAM_A[8..7]
tVXCI1
10
tVXCI2
VID_CLK
VID_CKE
Internal VID_CLK
tVQ
VID_Q Normal mode VID_Q Reversed mode
tVXQFI
Data 0
Data 1
Data 2
Data 3
Data 1
Data 0
Data 3
Data 2
VID_QSF
M1024
Note: 1. Note that the VID_OE is always "1" for video output enable is assumed. 2. Timings are measured from the MCLK pin or from the VID_CLK pin.
Figure 8.15 Video output sequence from intial VDX for normal and reversed modes
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Rev. 1.03 3D-RAM (M5M410092B)
Table 8.10 Video Buffer timing parameters M5M410092B Symbol tVCLK tVCLKH tVCLKL tVCES tVCEH tVQ tVQVC tVLZ tVHZ tVQE tVQVE tVXCI1 tVXCI2 tVXQFI Parameter VID_CLK cycle time VID_CLK high pulse width VID_CLK low pulse width VID_CKE setup time VID_CKE hold time VID_Q access time from VID_CLK VID_Q valid after VID_CLK VID_Q output low impedance VID_Q output high impedance VID_Q access time from VID_OE high VID_Q valid after VID_OE low Initial VDX after last internal VID_CLK Initial VDX before next internal VID_CLK VID_QSF delay time after initial VDX -10A, -10 -12 Unit Refer -- -- -- -- -- 8 -- -- 3 9 -- -- -- 80 ns ns ns ns ns ns ns ns ns ns ns ns ns ns t1 t2 t3 t8 t9 t11 t12 t16 t15 t17 t14 -- -- t11 Timing Figure 8.14 8.14 8.14 8.14 8.14 8.14 8.14 8.14 8.14 8.14 8.14 8.15 8.15 8.15
Min Max Min Max 12 5 5 4 0 -- 3 3 -- -- -- 14 80 -- -- -- -- -- -- 8 -- -- 3 9 -- -- -- 80 12 5 5 4 0 -- 3 3 -- -- -- 14 80 --
133
8 Timing Diagrams
ELECTRONIC DEVICE GROUP
MITSUBISHI
Rev. 1.03 3D-RAM (M5M410092B)
VID_QSF
tQSF tVQ tQSF
Bank 0 VID_Q [15 . . 0] 0 VID_CLK 0 1 1 2 37 37 38
Bank 1 0 1 1 2 37 38 38 39 39 0
Bank 2 0 1 1 2
38 39
39 0
VID_CKE
tVXC1 tVXC2
MCLK
DRAM_OP
VDX
VDX
VDX
DRAM_BS
0
1
2
DRAM_A [8 . . 7]
10
0x
0x
Initial VDX During Retrace
Normal VDX During Retrace
Normal VDX During Display
M1022
8 Timing Diagrams
Note: 1. tVXC1 specifies the earliest allowed normal VDX. 2. tVXC2 specifies the latest allowed normal VDX.
Figure 8.16 Continuous video output sequence in normal mode during display
Table 8.11 Video Buffer timing parameters M5M410092B Symbol tQSF tVXC1 tVXC2 Parameter VID_QSF delay time from internal VID_CLK 38 Normal VDX after internal VID_CLK 38 Normal VDX before next internal VID_CLK 38 -10A, -10 Min -- 20 60 Max 25 -- -- -12 Min Max -- 20 60 25 -- -- ns ns ns t11 -- -- Unit Refer
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Rev. 1.03 3D-RAM (M5M410092B)
tSCLK tSCLKH tSCLKL
SCAN_TCK
Controller State
Test-Logic Reset Note 1
Run-Test-Idle
Shift-IR
Shift-IR
Exit-IR
Update-IR
tSCNTS
tSCNTH
SCAN_TMS
tSCNIS tSCNIH
SCAN_TDI
tSQ tSHZ
SCAN_TDO
tSLZ tSVD
M1004
Figure 8.17 Boundary scan
M5M410092B -10A, -10, -12 Symbol tSCLK tSCLKH tSCLKL tSCNTS tSCNTH tSCNIS tSCNIH tSLZ tSQ tSVD tSHZ Parameter SCAN_TCK cycle time SCAN_TCK high pulse width SCAN_TCK low pulse width SCAN_TMS setup time SCAN_TMS hold time SCAN_TDI setup time SCAN_TDI hold time SCAN_TCK to SCAN_TDO low impedance SCAN_TDO access time SCAN_TDO data valid time SCAN_TCK to SCAN_TDO high impedance Min 100 40 40 8 26 8 26 -- -- 8 -- Max -- -- -- -- -- -- -- 20 26 -- 20 Unit Refer ns ns ns ns ns ns ns ns ns ns ns t1 t2 t3 t8 t9 t8 t9 t18 t19 t20 t21
135
8 Timing Diagrams
Table 8.12 Boundary-Scan timing parameters
ELECTRONIC DEVICE GROUP
MITSUBISHI
Rev. 1.03 3D-RAM (M5M410092B)
SCAN_TCK
tSCNRP tSCNRS
SCAN_RST
M1005
Figure 8.18 Boundary scan reset
Table 8.13 Boundary-Scan reset timing parameters M5M410092B -10A, -10, -12 Min tSCNRS tSCNRP SCAN_RST setup time SCAN_RST pulse width 8 30 Max -- -- ns ns t6 t7
Symbol
Parameter
Unit Refer
8 Timing Diagrams
136
9
Packaging
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Rev. 1.03 3D-RAM (M5M410092B)
Packaging
The 3D-RAM is housed in 128-pin QFP(FP) and reverse QFP(RF) packages. For the purpose of convenient reference, the pinout diagrams for the 3D-RAM are repeated on pages 137 and 138. Page 103 contains the mechanical specification for the FP and RF packages. The thermal characteristics data for both packages is on page 142.
3D-RAM Pinouts
There are two pinouts for 3D-RAM: normal pinout with pin 1 located at the lower left hand corner and specially marked by a small circle; and reverse pinout with pin 1 located at the upper left hand corner and marked by a large circle and a pointing triangle. The device in normal pinout is designated by the letters "FP" in the product number, and the device in reverse pinout by the letters "RF." In both pinouts, the mapping of pin numbers with pin names is identical.
Normal Pinout Diagram
PALU_DQ30 106 PALU_DQ31 107 PALU_DQ29 VDD 103 PALU_DQ28 104 DRAM_OP2 121 DRAM_A6 122 DRAM_OP1 DRAM_BS0 125 DRAM_BS1 126 VSS 112 PALU_OP2 113 PALU_EN1 115 PALU_A3 116 PALU_DX3 109 PALU_BE2 110 PALU_DX2 PALU_BE3 PALU_WE 114 DRAM_A7 123 DRAM_A8 124 PALU_A4 117 PALU_A5 118 RESET 127
VDD 128
VSS 119
120
111
108
105
SCAN_TMS SCAN_TCK SCAN_RST VID_Q8 VID_Q9 VSS VID_Q10 VID_Q11 VID_Q12 VID_Q13 VDD VID_Q14 VID_Q15 VID_QSF VID_CKE VSS VSS PASS_IN0 VDD VID_CLK VSS PASS_IN1 VSS VID_OE HIT VID_Q0 VID_Q1 VDD VID_Q2 VID_Q3 VID_Q4 VID_Q5 VSS VID_Q6 VID_Q7 SCAN_TDO SCAN_TDI VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
102 VDD 101 PALU_DQ27 100 PALU_DQ26 99 PALU_DQ25 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PALU_DQ24 VSS PALU_DQ23 PALU_DQ22 PALU_DQ21 PALU_DQ20 VDD PALU_DQ19 PALU_DQ18 PALU_DQ17 PALU_DQ16 VSS PASS_OUT VDD MCLK NC VSS VSS PALU_DQ15 PALU_DQ14 PALU_DQ13 PALU_DQ12 VDD PALU_DQ11 PALU_DQ10 PALU_DQ9 PALU_DQ8 VSS PALU_DQ7 PALU_DQ6 PALU_DQ5 PALU_DQ4 VDD
M5M410092BFP
DDDMMMMM-nn
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
M1048
137
9 Packaging
16
VSS
39 VDD
40 DRAM_A0
41 DRAM_A1
42 DRAM_A2
43 DRAM_A3
44 DRAM_A4
45
46
47 DRAM_OP0
48 VSS
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
DRAM_EN DRAM_A5
PALU_A0
PALU_A1
PALU_A2
PALU_EN0
PALU_OP0
VSS PALU_OP1
PALU_BE0
PALU_BE1
PALU_DX0
PALU_DX1
PALU_DQ0
PALU_DQ1
PALU_DQ2
VDD PALU_DQ3
ELECTRONIC DEVICE GROUP
MITSUBISHI
Rev. 1.03 3D-RAM (M5M410092B)
Reverse Pinout Diagram
PALU_DQ29 105 PALU_DQ28 104 PALU_DQ30 PALU_DQ31
DRAM_OP2 121 DRAM_OP1 120
DRAM_BS1 126 DRAM_BS0 125
PALU_WE 114 PALU_OP2 113
PALU_EN1
PALU_DX3 109 PALU_DX2 108
PALU_BE3 111 PALU_BE2 110
DRAM_A8 124 DRAM_A7 123
DRAM_A6
PALU_A4 117 PALU_A3 116
VSS 119 PALU_A5 118
RESET 127
VDD 128
VDD 103
VSS 112
106
107
115
122
VDD 102 PALU_DQ27 101 PALU_DQ26 100 PALU_DQ25 PALU_DQ24 VSS PALU_DQ23 PALU_DQ22 PALU_DQ21 PALU_DQ20 VDD PALU_DQ19 PALU_DQ18 PALU_DQ17 PALU_DQ16 VSS VSS PASS_OUT VDD MCLK NC VSS VSS PALU_DQ15 PALU_DQ14 PALU_DQ13 PALU_DQ12 VDD PALU_DQ11 PALU_DQ10 PALU_DQ9 PALU_DQ8 VSS PALU_DQ7 99 98 97 96 95 94 93 92 91 90 89 88
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
SCAN_TMS SCAN_TCK SCAN_RST VID_Q8 VID_Q9 VSS VID_Q10 VID_Q11 VID_Q12 VID_Q13 VDD VID_Q14 VID_Q15 VID_QSF VID_CKE VSS VSS PASS_IN0 VDD VID_CLK VSS PASS_IN1 VSS VID_OE HIT VID_Q0 VID_Q1 VDD VID_Q2 VID_Q3 VID_Q4 VID_Q5 VSS VID_Q6 VID_Q7 SCAN_TDO SCAN_TDI VDD
M5M410092BRF
DDDMMMMM-nn
87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
9 Packaging
PALU_DQ6 PALU_DQ5 PALU_DQ4 VDD
64 VDD
63 PALU_DQ3
62 PALU_DQ2
61 PALU_DQ1
60 PALU_DQ0
59 PALU_DX1
58 PALU_DX0
57 PALU_BE1
56
55
54 PALU_OP1
53 PALU_OP0
52
51
50
49
48
47
46
45
44
43
42
41
40
39
VDD DRAM_A0
VSS PALU_A0
DRAM_EN DRAM_OP0
DRAM_A5
DRAM_A4
DRAM_A3
DRAM_A2
DRAM_A1
VSS PALU_BE0
PALU_EN0
PALU_A2
PALU_A1
M1003
Tracking Label
On the top surface of the 3D-RAM package, a tracking label is printed below the Mitsubishi logo and the 3D-RAM product number. The tracking label consists of 7 numbers followed by a dash and a speed/power grade designation, and is represented by the mnemonic "DDDMMMMM-nn". This mnemonic is explained as below:
DDD: Date code MMMMM: Manufacturing code nn: One of the following speed designations: "10A" -- tCLK (min) = 10 ns "10" -- tCLK (min) = 10 ns except tCLK (min) = 12 ns for the alpha saturate logic "12" -- tCLK (min) = 12 ns
138
ELECTRONIC DEVICE GROUP
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Rev. 1.03 3D-RAM (M5M410092B)
Mechanical Drawing for 128-pin FP and RF Packages
HD D
128 103
A2
A1 e
1
102
ME
b2
M5M410092FP M5M410092BFP
I2 E HE MD
Recommended Mount Pad
38
65
39
64
SEATING PLANE c A
L1
SEATING PLANE e y b SEE DETAIL F
L
DETAIL F
M1041
Figure 9.1 128-pin FP package drawing
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ELECTRONIC DEVICE GROUP
MITSUBISHI
Rev. 1.03 3D-RAM (M5M410092B)
HD D
103 128
A2
A1 e
102
1
ME
b2
M5M410092BRF
I2 E HE MD
Recommended Mount Pad
65
38
64
39
SEATING PLANE c A
L1
SEATING PLANE e b SEE DETAIL F
L
9 Packaging
y
DETAIL F
M1042
Figure 9.2 128-pin RF package drawing
140
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Rev. 1.03 3D-RAM (M5M410092B)
Table 9.1 Package drawing parameters in millimeters
Dimension in Millimeters Description
Mounting height Stand-off height Package height Terminal width Terminal thickness Package length Package width Linear spacing between terminals Over length Over width Length of the flat portion of terminal Terminal length Flatness of terminal Terminal angle Mount pad dimensions Mount pad dimensions Mount pad dimensions Mount pad dimensions
Symbol
A A1 A2 b c D E e HD HE L L1 y q b2 I2 MD ME
Min
-- 0.05 -- 0.13 0.105 13.9 19.9 -- 15.8 21.8 0.3 -- -- 0 -- 1.0 -- --
Nominal
-- 0.15 1.4 0.18 0.125 14.0 20.0 0.5 16.0 22.0 0.5 1.0 -- -- 0.225 -- 14.4 20.4
Max
1.7 0.25 -- 0.28 0.175 14.1 20.1 -- 16.2 22.2 0.7 -- 0.1 10 -- -- -- --
141
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ELECTRONIC DEVICE GROUP
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Rev. 1.03 3D-RAM (M5M410092B)
and Ta is the ambient temperature. Thermal Resistance for Single Package Four cases of the thermal resistance for single package are listed in Table 9.2. These four cases are package only, package on PCB, package on PCB with thermal compound, and package on PCB with fin. Figures 9.3 through 9.7 show the detailed conditions of these four cases.
Thermal Characteristics
The maximum junction temperature (Tjc) is set to 125 C. The junction temperature can be calculated with the following equation: Tjc (C) = ja (C/W) x P (W) + Ta (C) where ja is the junction-to-ambient thermal resistance, P is the whole chip power dissipation, Table 9.2 Thermal resistance for single package
Case 2 Case 1 Package only Package on PCB Airflow
0; or natural convection 100 ft/min or 0.5 m/s 200 ft/min or 1.0 m/s 400 ft/min or 2.0 m/s 1000 ft/min or 5.0 m/s
Case 3 Package on PCB with compound
Case 4 Package on PCB with fin
ja (C/W)
160.0 97.0 78.0 59.5 43.1
ja (C/W)
86.0 66.2 58.7 49.4 39.5
ja (C/W)
80.0 60.3 53.9 43.6 35.1
ja (C/W)
44.4 31.2 26.3 20.9 16.2
Package
Thermal Compound
Package
9 Packaging
PCB (Adiabatic Plane)
Figure 9.3 Case 1 condition: package only
(Adiabatic Plane)
Figure 9.5 Case 3 condition: package on PCB with thermal compound
Fin Package 9.2 mm Package
PCB (Adiabatic Plane)
Figure 9.4 Case 2 condition: package on PCB
PCB (Adiabatic Plane)
Figure 9.6 Case 4 condition: package on PCB with fin
142
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Rev. 1.03 3D-RAM (M5M410092B)
1.0
2.0
7.5 9.2
1.5
1.5
 13
6
Figure 9.7 Mechanical drawing of the fin
143
9 Packaging
ELECTRONIC DEVICE GROUP
MITSUBISHI
Rev. 1.03 3D-RAM (M5M410092B)
Thermal Resistance for Twelve Packages Mounted on PCB Table 9.3 lists the thermal resistance for 12 packages mounted on two sides of a PCB. Two cases are listed: without heat sink and with aluminum plate for heat sink. Table 9.3 Thermal resistance for 12 packages mounting double-sided on PCB Without Heat Sink With Heat Sink
Solder Fe
PCB
Airflow
0 m/s or natural convection 100 ft/min or 0.5 m/s 200 ft/min or 1.0 m/s 400 ft/min or 2.0 m/s 1000 ft/min or
ja (C/W)
84.0
ja (C/W)
41.0
Figure 9.8 Multiple packages double-side mounted on PCB, without heat sink
Al Plate (40 x 20 x 0.6 mm)
73.0 26.1
Resin
59.2 21.5
Solder Fe PCB
43.8
17.0
Figure 9.9 Multiple packages double-side mounted on PCB, with heat sink
30.7
13.3
9 Packaging
5.0 m/s
144
ELECTRONIC DEVICE GROUP
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Rev. 1.03 3D-RAM (M5M410092B)
PCB (Glass Epoxy)
Air Flow 10.16
76.2
1.6
Figure 9.10 Mechanical drawing of the mounting, without heat sink
145
9 Packaging
ELECTRONIC DEVICE GROUP
MITSUBISHI
Rev. 1.03 3D-RAM (M5M410092B)
Al Resin 0.6
Air Flow 10.16
MAX 2.5
40
20 76.2 1.6
Figure 9.11 Mechanical drawing of the mounting, with heat sink
9 Packaging
146
10
JTAG Boundary Scan
ELECTRONIC DEVICE GROUP
MITSUBISHI
Rev. 1.03 3D-RAM (M5M410092B)
JTAG Boundary Scan
Boundary-Scan Architecture
The 3D-RAM provides test features that are partially in compliance with the IEEE Standard 1149.1 Test Access Port and Boundary-Scan Architecture. The on-chip test logic provides a standardized approach for checking the interconnections between different components on the same printed circuit board. The boundary-scan test logic consists of the boundary-scan register and support logic. The test function is accessed through the Test Access Port (TAP). The TAP provides a simple serial interface that allows testing of all signal traces with only five pins in the Serial Test Port. Inside the 3D-RAM, the boundary-scan cells for the signal pins are interconnected to form a shiftregister chain around the pads. This path has serial input and output connections with scan clock and control signals. On a printed circuit board, the boundary-scan registers for the individual components can be connected in series to form a single path through the whole board, as illustrated in Figure 10.1. Alternatively, a board design could contain several independent boundary-scan paths.
Boundary-scan cell
Serial data in
Serial data out
Serial test interconnect
System interconnect
Figure 10.1 A boundary-scannable board design
147
10 JTAG Boundary Scan
ELECTRONIC DEVICE GROUP
MITSUBISHI
Rev. 1.03 3D-RAM (M5M410092B)
instruction codes shifted through the test data input (SCAN_TDI) pin * Two test Data Registers: Bypass Register (BPR) and Boundary-Scan Register (BSR) The instruction and test data registers are separate shift-register paths connected in parallel and have a common serial data input (SCAN_TDI) and a common serial data output (SCAN_TDO). The data flow is controlled by the TAP controller signals. A block diagram of the boundary-scan architecture is shown in Figure 10.2.
The boundary-scan test logic contains the following elements: * Test Access Port (TAP), consisting of input pins SCAN_TMS, SCAN_TCK, SCAN_RST and SCAN_TDI, and an output pin SCAN_TDO * TAP Controller, which interprets the inputs on the test mode select line (SCAN_TMS) and performs the corresponding operations, such as controlling the scan instruction and data registers within the 3D-RAM * Instruction Register (IR), which accepts
Boundary Scan Register
SCAN_TDI
Bypass Register Decode Instruction Register
SCAN_TDO
Clocks and/or Controls
10 JTAG Boundary Scan
TAP Controller SCAN_TMS SCAN_TCK SCAN_RST
M1002
Figure 10.2 Block diagram of the boundary scan architecture
148
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Rev. 1.03 3D-RAM (M5M410092B)
controller is shown in Figure 10.3. The TAP controller is initialized either after power up or when SCAN_RST is asserted low. In addition, it can be initialized by applying a high signal level on the SCAN_TMS input for five SCAN_TCK cycles.
The TAP Controller
The TAP controller is a synchronous finite state machine controlling the sequence of test logic operations. The TAP controller changes state at the rising edge of the SCAN_TCK pin. The SCAN_TMS pin controls the sequence of the state changes. A state diagram for the TAP
1
Test-LogicReset 0
0
Run-Test/ Idle
1
SelectDR-Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0
1
SelectIR-Scan 0 1 Capture-IR 0 0 Shift-IR 1
1
0
0 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 0
Figure 10.3 TAP controller state diagram
149
10 JTAG Boundary Scan
1
Exit1-IR
1
ELECTRONIC DEVICE GROUP
MITSUBISHI
Pause-DR State
Rev. 1.03 3D-RAM (M5M410092B)
Test-Logic-Reset State The Instruction Register is set to the default Bypass instruction, so that normal 3D-RAM operations can proceed without interference. The TAP controller enters this state when it is initialized after power-up or by the reset signal SCAN_RST. Regardless of the original state, the controller enters this state when the SCAN_TMS input is held high for at least five rising SCAN_TCK cycles. Run-Test/Idle State This is an idle state. The test data register selected by the current instruction retains its previous value during this state. The current instruction does not change in this state. Select-DR-Scan State This is a temporary controller state. The test data register selected by the current instruction retains its previous value during this state. The current instruction does not change in this state. Capture-DR State
The Pause-DR state allows the data shifting through the test data register to be temporarily halted. The test data register selected by the current instruction retains its previous value during this state. The current instruction does not change in this state. Exit2-DR State This is a temporary controller state. The test data register selected by the current instruction retains its previous value during this state. The current instruction does not change in this state. Update-DR State The boundary-scan cell for output pad has a latch to prevent changes at the parallel output while data is shifting along the boundary-scan chain. When the TAP controller is in this state and the Boundary-Scan Register is selected, data is latched from the shift-register path on the falling edge of SCAN_TCK. The data held at the latch does not change other than in this state. All shiftregister stages in selected test data register retain their previous values during this state. The current instruction does not change in this state. Select-IR-Scan State This is a temporary controller state. The test data register selected by the current instruction retains its previous state. The current instruction does not change in this state. Capture-IR State The shift-register contained in the Instruction Register is loaded with the fixed value "1001" on the rising edge of SCAN_TCK. The test data register selected by the current instruction retains its previous value during this state. The current instruction does not change in this state.
10 JTAG Boundary Scan
The Boundary-Scan Register captures input data from the SCAN_TDI pin if the current instruction is Extest or Sample/Preload. The Bypass Register does not change. The current instruction does not change in this state. Shift-DR State The test data register selected by the current instruction shifts data one stage toward SCAN_TDO on each rising edge of SCAN_TCK. The current instruction does not change in this state. Exit1-DR State This is a temporary controller state. The test data register selected by the current instruction retains its previous value during this state. The current instruction does not change in this state.
150
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Rev. 1.03 3D-RAM (M5M410092B) Test Data Register
The 3D-RAM contains the two required test data registers: Bypass Register and Boundary-Scan Register. Both registers are connected to the SCAN_TDI and SCAN_TDO pins. When a register is selected by the current instruction, the data in its shift-register is shifted one stage towards the SCAN_TDO output pin on each rising edge of the SCAN_TCK pin. Bypass Register The Bypass Register is a one-bit shift-register that provides the minimal length path between the SCAN_TDI and SCAN_TDO pins. When the 3D-RAM is not required to perform scan test operation, this path can be selected to allow rapid movement of test data to and from other components on the board. Boundary-Scan Register The Boundary-Scan Register is a shift-register path containing the boundary-scan cells that are connected to all input/output signal pins of the 3D-RAM except the following pins: MCLK, PASS_IN[1:0], PASS_OUT, and VID_CLK. The boundary-scan cells of the PALU_DQ[31:0] pins are implemented as input pins only. Figure 10.4 shows the logical structure of the Boundary-Scan Register. While output cells determine the value of the signal driven on the corresponding pin, input cells only capture data. The output cell has a latch connected to the shift-register for latching the data in Update-DR state. These operations do not affect the normal operations of the device. Data is shifted from the SCAN_TDI pin to the SCAN_TDO pin through the Boundary-Scan Register during scanning. The Boundary-Scan Register can be operated by the Extest and Sample/Preload instructions.
Shift-IR State The shift-register contained in the Instruction Register is connected between the SCAN_TDI and SCAN_TDO pins. The shift-register shifts data one stage towards its serial output on each rising edge of SCAN_TCK. The test data register selected by the current instruction retains its previous value during this state. The current instruction does not change in this state. Exit1-IR State This is a temporary state. The test data register selected by the current instruction retains its previous value during this state. The current instruction does not change in this state. Pause-IR State The Pause-IR state allows the data shifting through the Instruction Register to be temporarily halted. The test data register selected by the current instruction retains its previous value during this state. The current instruction does not change in this state. Exit2-IR State This is a temporary state. The test data register selected by the current instruction retains its previous value during this state. The current instruction does not change in this state. Update-IR State The instruction shifted into the Instruction Register is latched from the shift-register path on the falling edge of SCAN_TCK. The test data register selected by the current instruction retains its previous value during this state. Once the new instruction has been latched, it becomes the current instruction.
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10 JTAG Boundary Scan
ELECTRONIC DEVICE GROUP
MITSUBISHI
Rev. 1.03 3D-RAM (M5M410092B)
RESET, PALU_DQ, PALU_DX, PALU_A, PALU_OP, PALU_BE, PALU_EN, DRAM_A, DRAM_BS, DARM_OP, DRAM_EN, VID_CKE
B/S Cell
B/S Cell
VID_QSF
B/S Cell
VID_Q
3D-RAM System Logic
B/S Cell VID_Q
VID_OE
B/S Cell
B/S Cell
HIT
10 JTAG Boundary Scan
M1001
Figure 10.4 Logical structure of the Boundary-Scan Register
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Rev. 1.03 3D-RAM (M5M410092B)
The boundary-scan cells inside the Boundary-Scan Register are organized in the following order:
Instruction Register
The Instruction Register (IR) allows instructions to be serially shifted into the 3D-RAM through the SCAN_TDI pin. The instruction selects the particular test to be performed, the test data register to be accessed, or both. The instruction register is a four-bit wide shift-register with a parallel latch. The most significant bit is connected to the SCAN_TDI pin and the least significant bit is connected to the SCAN_TDO pin. On entering
the Capture-IR controller state, the Instruction Register is loaded with the default instruction "1001", which is the Bypass instruction. Instructions are shifted into the Instruction Register on the rising edge of the SCAN_TCK pin while the TAP controller is in the Shift-IR state. The 3D-RAM supports all three mandatory boundary-scan instructions, namely Bypass, Sample/Preload, and Extest. Table 10.1 lists the 3D-RAM boundary-scan instruction codes.
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SCAN_TDI DRAM_A3 DRAM_OP0 PALU_EN0 PALU_BE1 PALU_DQ1 PALU_DQ5 PALU_DQ9 PALU_DQ13 PALU_DQ17 PALU_DQ21 PALU_DQ25 PALU_DQ29 PALU_DX3 PALU_WE PALU_A5 DRAM_A7 RESET VID_Q11 VID_Q15 HIT VID_Q3 VID_Q7
                      
DRAM_A0 DRAM_A4 PALU_A0 PALU_OP0 PALU_DX0 PALU_DQ2 PALU_DQ6 PALU_DQ10 PALU_DQ14 PALU_DQ18 PALU_DQ22 PALU_DQ26 PALU_DQ30 PALU_BE2 PALU_EN1 DRAM_OP1 DRAM_A8 VID_Q8 VID_Q12 VID_QSF VID_Q0 VID_Q4 SCAN_TDO
                     
DRAM_A1 DRAM_A5 PALU_A1 PALU_OP1 PALU_DX1 PALU_DQ3 PALU_DQ7 PALU_DQ11 PALU_DQ15 PALU_DQ19 PALU_DQ23 PALU_DQ27 PALU_DQ31 PALU_BE3 PALU_A3 DRAM_OP2 DRAM_BS0 VID_Q9 VID_Q13 VID_CKE VID_Q1 VID_Q5
                     
DRAM_A2 DRAM_EN PALU_A2 PALU_BE0 PALU_DQ0 PALU_DQ4 PALU_DQ8 PALU_DQ12 PALU_DQ16 PALU_DQ20 PALU_DQ24 PALU_DQ28 PALU_DX2 PALU_OP2 PALU_A4 DRAM_A6 DRAM_BS1 VID_Q10 VID_Q14 VID_OE VID_Q2 VID_Q6
                     
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The instruction code is "0100". The Sample/ Preload instruction allows the scanning of the Boundary-Scan Register without interference to the normal operation of the 3D-RAM. As suggested by the instruction name, the Sample/ Preload instruction can be used to perform two functions: * SAMPLE is performed in the Capture-DR controller state. All signals received at the 3D-RAM input pins are loaded into the Boundary-Scan Register on the rising edge of the SCAN_TCK pin. * PRELOAD is performed in the Update-DR controller state. The data held in the shiftregister stage of the output cell is latched on the falling edge of the SCAN_TCK pin. Extest Instruction The instruction code is "0000". The Extest instruction allows testing of board interconnections. The Extest instruction selects the Boundary-Scan Register to be connected between the SCAN_TDI and SCAN_TDO pins. Two functions are performed when the Extest instruction is selected: * In the Capture-DR controller state, all signals received at the 3D-RAM input pins are loaded into the Boundary-Scan Register on the rising edge of the SCAN_TCK pin. This is equivalent to the Sample operation in the Sample/Preload instruction. * In the Update-DR controller state, the data held in the shift-register stage of the output cell is latched and driven to the 3D-RAM output pins, on the falling edge of the SCAN_TCK.
Table 10.1 Boundary-Scan instruction codes Instruction Code
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Instruction Name
Extest Bypass Bypass Bypass Sample/Preload Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass
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Bypass Instruction The instruction codes for the Bypass instruction are any codes except "0000" (for Extest) and "0100" (for Sample/Preload). The Bypass instruction selects the Bypass Register to be connected to the SCAN_TDI or SCAN_TDO pin. The Bypass Register contains a single shiftregister stage and is used to provide a minimum length serial path between the SCAN_TDI and the SCAN_TDO pins when no scan test operation of the 3D-RAM is required. This allows more rapid movement of test data to and from other components on the board. Due to the pull-up resistor on the SCAN_TDI input, an open circuit fault in the board level test data path will cause the Bypass Register to be selected following an instruction scan cycle. This was done to prevent any unwanted interference with the normal operation of the 3D-RAM. Sample/Preload Instruction
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into the shift-register on the rising edge of the SCAN_TCK pin. * In the Update-DR controller state, the data held in the shift-register is latched on the falling edge of the SCAN_TCK pin. If the instruction is Extest, the latched VID_OE data will control the tri-state buffer of the VID_Q bus.
VID_OE Boundary-Scan Cell
The VID_OE pin controls the tri-state buffer of the VID_Q bus. Therefore, its boundary-scan cell configuration is different from a normal input pin. The functions performed on this cell for the Sample/Preload and Extest instructions are summarized below. * In the Capture-DR controller state, the signal received at the VID_OE pin is loaded
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Formal Specification of Operations
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Formal Specification of Operations
This chapter specifies exactly which bits are moved for many types of operations. It uses a syntax derived from C and Verilog to specify exactly which bits are copied for each operation.
Elements
bit DA[4][257][10240] bit SA[4][10240] bit RAL[4][9] bit VB[2][640] bit VD[16] bit VC[7] bit VM[1] bit SRAM[8][256] bit DT[8][32] bit PM[32] bit DQ[32] bit BE[4] bit daddr[9] bit paddr[6] DRAM Array Sense Amplifiers Row Address Latch Video Buffer Video Data pins Video Counter Video Mode Static RAM Dirty Tag Plane Mask register Pixel ALU data pins Byte Enable pins DRAM address Pixel ALU address
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Bit Ordering of Elements
Block PALU_DQ pins
0 64
8 72
16 80
24 88
32
40
48
56 0 8 16 24
96 104 112 120
128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248
PALU_BE pins
0 1 2 3
Plane Mask
Page
0 8 16 24
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0
8
16
616 624 632 1256 1264 1272
Dirty Tags
0 2 8 10 12 14 16 18 20 22 24 26 28 30 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
640 648 656
8960 8968 8976 9600 9608 9616
9576 9584 9592 10216 10224 10232
4 6
Video Buffer
VID_Q pins
0
8
16
616 624 632
0
8
Figure 11.1 Bit orderings of several elements
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Blocks within a Page
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Words within a Block
0 2 4 6
1 3
7 Figure 11.2 Orderings of words and blocks in a page
Access Page
ACCESS PAGE(bit bank[2], bit daddr[9]) { bit i[4]; for(i = 0; i < 9; i++) RAL[bank][i] <- daddr[i]; bit j[14]; for(j = 0;j < 10240; j++) SA[bank][j] <- DA[bank][daddr][j]; }
Duplicate Page
DUPLICATE PAGE(bit bank[2], bit daddr[9]) { bit i[4]; for(i = 0; i < 9; i++) RAL[bank][i] <- daddr[i]; bit j[14]; for(j = 0;j < 10240; j++) DA[bank][daddr][j] <- SA[bank][j]; }
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Precharge Bank
PRECHARGE(bit bank[2]) {}
Read Block
READ BLOCK(bit bank[2], bit daddr[9]) { bit i[8]; for(i = 0; i < 256; i++) SRAM[daddr[8..6]][i] <- SA[bank][daddr[1..0]*2560 + i[7..6]*640 + daddr[5..2]*64 + i[5..0]]; bit j[5]; for(j = 0;j < 32; j++) DT[daddr[8..6]][j] <- 0; }
Masked Write Block
MASKED WRITE BLOCK(bit bank[2], bit daddr[9]) {
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bit i[8]; for(i = 0; i < 256; i++) if(PM[i[4..0]] && DT[daddr[8..6]][{i[4..3],i[7..5]}]) { SA[bank][daddr[1..0]*2560 + i[7..6]*640 + daddr[5..2]*64 + i[5..0]] 160
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Unmasked Write Block
UNMASKED WRITE BLOCK(bit bank[2], bit daddr[9]) { bit i[8]; for(i = 0; i < 256; i++) if(DT[daddr[8..6]][{i[4..3],i[7..5]}]) { SA[bank][daddr[1..0]*2560 + i[7..6]*640 + daddr[5..2]*64 + i[5..0]] Video Transfer
VIDEO TRANSFER(bit bank[2], bit daddr[9]) { bit i[10]; for(i = 0; i < 640; i++) VB[bank[0]][i] <- SA[bank][640*daddr[3..0] + i]; if(daddr[8]) { VC[5..0] <- 0; VC[6] <- bank[0]; VM[0] <- daddr[7]; } }
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Video Cycle
VIDEO CYCLE(bit enable[1], bit voe[1]) { if(voe) { bit i[4]; for(i = 0; i < 16; i++) VD[i] <- VB[VC[6]][{VC[5..1],(VC[0]^VM[0])}*16 + i]; } if(enable) { if(VC[5..0] == 39) { VC[5..0] <- 0; VC[6] <- ~VC[6]; } else { VC[5..0] <- VC[5..0] + 1;
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} } }
Data Read
DATA READ(bit paddr[6]) { bit i[5]; for(i = 0; i < 32; i++) if(BE[i[4..3]]) DQ[i] <- SRAM[paddr } [5..3]][paddr[2..0]*32 + i];
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Stateless Initial Data Write
STATELESS INITIAL DATA WRITE(bit paddr[6]) { bit i[5]; for(i = 0; i < 32; i++) if(BE[i[4..3]]) SRAM[paddr[5..3]][paddr[2..0]*32 + i] <- DQ[i]; bit j[5]; for(j = 0;j < 32; j++) if (CDS[0] == 0) /* (8,8,8,8) normal mode */ if((paddr[2..0] == j[2..0]) && BE[j[4..3]]) DT[paddr[5..3]][j] <- 1; else DT[paddr[5..3]][j] <- 0; else /* (4,4,4,4) 16-bit color mode */
ERROR("illegal byte enable combination"); else if((paddr[2..0] == j[2..0]) && j[4]) DT[paddr[5..3]][j] <- (BE[3] || BE[1]); else if((paddr[2..0] == j[2..0] && !j[4]) DT[paddr[5..3]][j] <- (BE[2] || BE[0]); else DT[paddr[5..3]][j] <- 0;) }
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if(((BE[3] || BE[2]) == 1) && ((BE[1] || BE[0]) == 1))
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Stateless Normal Data Write
STATELESS NORMAL DATA WRITE(bit paddr[6]) { bit i[5]; for(i = 0; i < 32; i++) if(BE[i[4..3]]) SRAM[paddr[5..3]][paddr[2..0]*32 + i] <- DQ[i]; bit j[5]; for(j = 0; j < 32; j++) if (CDS[0] == 0) /* (8,8,8,8) normal mode */ if((paddr[2..0] == j[2..0]) && BE[j[4..3]]) DT[paddr[5..3]][j] <- 1; else /* (4,4,4,4) 16-bit color mode */ if(((BE[3] || BE[2]) == 1) && ((BE[1] || BE[0]) == 1)) ERROR("illegal byte enable combination");
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else if((paddr[2..0] == j[2..0]) && j[4]) DT[paddr[5..3]][j] <- (BE[3] || BE[1]); else if((paddr[2..0] == j[2..0] && !j[4]) DT[paddr[5..3]][j] <- (BE[2] || BE[0]); }
Replace Dirty Tag
REPLACE DIRTY TAG(bit paddr[6]) { bit i[5]; for(i = 0; i < 32; i++) if(BE[i[4..3]]) if (i == paddr[2..0] + 8*i[4..3]) DT[paddr[5..3]][i] <- DQ[i]; }
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OR Dirty Tag
OR DIRTY TAG(bit paddr[6]) { bit i[5]; for(i = 0; i < 32; i++) if(BE[i[4..3]] && DQ[i]) if (i == paddr[2..0] + 8*i[4..3]) DT[paddr[5..3]][i] <- DQ[i]; }
Write Plane Mask Register
WRITE PLANE MASK REGISTER() { bit i[5]; for(i = 0; i < 32; i++) if(BE[i[4..3]]) PM[i] <- DQ[i]; }
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Appendix A
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Appendix A
Glossary
Some of the terms used in this document may be unfamiliar to the reader, and some may have a specific meaning in the context of this document. For convenience, these terms are collected here and provided with a brief definition and a reference to the paragraphs where the terms are explained in greater detail. This glossary list is not intended to be exhaustive
3D-RAM An innovative 10-Mbit cached dual-port CMOS memory device that dramatically improves the performance of a three-dimensional computer graphics system with on-chip support for Z-buffer hidden surface removal algorithm and for full blending and logical raster operations, achieving a peak bandwidth of 14.6 Gbytes/s and a sustained bandwidth of 400 Mbytes/s (for the -10 speed grade). Blending A computer graphics operation for simulating the visual effect of overlapping objects with the foreground objects being partially transparent. An example of blending equations is that overall color = (a) x (color of foreground object) + (1 - a) x (color of background object), where a is the percentage of light transmitted through the medium of the foreground object. Each of the four 8-bit Blend units in the Pixel ALU can perform one of the two multiplications and then the addition, provided that the product of the other multiplication is supplied by the rendering controller. (Pages 10 and 26) Block A unit of memory organized into eight 32-bit words. This is the unit of data movement between a DRAM bank and the Pixel Buffer. (Pages 4 and 21)
Byte A unit of memory containing 8 bits of data. This is the unit of data operation for the four Blend units in the Pixel ALU. The rendering controller can enable or disable the writing (to 3D-RAM) or reading (from 3D-RAM) of the individual bytes in a word. (Pages 10, 15, and 26) Color Buffer The collection of memory that contains all color bits of all pixels to be displayed on the screen. Because the alpha information is needed for blending operations in 3D-RAM, the alpha data should also be stored together with the color data. It is also popular to have overlay information stored together with the color information to allow fast display of 2D objects by data multiplexing in a RADMAC chip. (Chapter 6) Dirty Tag A 32-bit memory in the Pixel Buffer, indicating which of the 32 bytes in the corresponding 256-bit block in the SRAM cache have been updated by the Pixel ALU since the data was transferred from the DRAM array. A "1" in a bit of Dirty Tag indicates the corresponding byte in the SRAM cache is newer than the data in the DRAM array. There are eight such Dirty Tags in the Pixel Buffer. (Page 22)
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each of the R, G, and B color component, bits for the Z (or depth) value, bits for window ID, and bits for some other auxiliary functions, such as overlay; only the color bits are actually displayed on the screen, while the other bits are stored with the color bits for faster graphic processing. (Chapter 6) Global Bus A 50-MHz (for the -10 speed grade) 256-bit data bus connecting between the four DRAM banks and the Pixel Buffer. (Page 8) Magitude Compare Pixel ALU operation that compares the incoming 32-bit data with the 32-bit data stored in the frame buffer. Each bit of the 32-bit magnitude comparison may be masked by setting a "1" in the corresponding bit of the Magnitude Mask register. The result of one of eight possible magnitude comparison tests can govern whether the new data is written into the frame buffer. Most commonly, as part of the Z-buffer hidden surface removal algorithm, the magnitude comparison tests are performed on the Z value of the existing pixel against that of a new pixel intended for the same screen location. (Pages 10, 51 and 61) Match Compare A Pixel ALU operation that compares the incoming 32-bit data with the 32-bit data stored in the frame buffer. Each bit of the 32-bit match comparison may be masked by setting a "1" in the corresponding bit of the Match Mask register. The result of one of four possible match comparison tests can govern whether the new data is written into the frame buffer. (Pages 10, 51 and 61) Page A unit of memory contains forty 256-bit blocks. Three DRAM operations (PRE, ACP, and DUP) operate on the entire 10,240-bit page in one command. (Pages 4 and 75)
In 2D rendering, this feature may also be used for color expansion from a bit to a byte to accelerate drawing of many pixels of the same color. Two Pixel ALU operations, namely "Replace Dirty Tags" and "Or Dirty Tags," may be used to facilitate this application of the Dirty Tags. (Page 23) In the (4, 4, 4, 4) 16-bit color mode, the setting of the dirty tag bits is same as the (8, 8, 8, 8) 32-bit color mode in the sense that if a byte of data is updated, then the corresponding dirty tag bit is set. However, since the PALU_BE[3:0] pins have different meanings in the (4, 4, 4, 4) 16-bit color mode from the (8, 8, 8, 8) 32-bit color mode, the specific dirty tag bits that are set are different in the two color modes. The mapping for the "Replace Dirty Tag" and "OR Dirty Tag" are the same in both modes. (Page 47) Double Buffer Two color buffers of identical size, with one of them shifting out video data toward the display screen (usually through a RAMDAC chip), while the other being updated with new pixel data by the rendering controller. (Pages 99 and 101) DRAM Bank One of the four 2.5-Mbit DRAM banks in a 3D-RAM chip. Each banks has 10,240 sense amplifiers, which function as a level-two pixel cache, and 257 pages of 10,240 bits each. All four DRAM banks are connected with a common 256-bit Global Bus to interface with the Pixel Buffer. (Page 6)
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Frame Buffer A collection of memory that contain all bits of data for all pixels in the display screen and, in some systems where the frame buffer is large enough to hold more than the pixel data for the specific display resolutions, extra pixel data temporarily stored outside the memory area for display pixels. A pixel data may include bits for the color value for
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resultant of the ROP/Blend units. For MBW, the effect of the Plane Mask on the (32-bit) word 0 is simply extended to words 1 through 7. (Pages 23 and 58) ROP An abbreviation for raster operation. There is a total of sixteen standard logical raster operations, including AND, OR, and XOR. (Pages 10, 26 and 60) Stateful Data Write A pixel data operation of the Pixel ALU. The word "stateful" refers to the controls of the Dual Compare units and the ROP/Blend units of the Pixel ALU on whether and what data is to be written into the Pixel Buffer. There are two types of Stateful Data Write: namely, Stateful Initial Data Write and Stateful Normal Data Write. (Page 66) Stateless Data Write A pixel data operation of the Pixel ALU. The word "stateless" refers to the straight pass-through of pixel data from the 3D-RAM inputs to the Pixel Buffer, with the data write unaffected by the ROP/ Blend units and the Dual Compare units of the Pixel ALU. There are two types of Stateless Data Write: namely, Stateless Initial Data Write and Stateless Normal Data Write. (Page 72) Stencil or Stenciling Stenciling applies a test that compares a reference value with the value stored at a pixel in the stencil buffer and then performs two tasks based on the results of this stencil test and the depth test: (1) operates on the update of the stencil data and (2) controls the write enable of the color buffer and the depth buffer. The most common use of stencil function is to generate an irregular shaped region of some desirable color pattern, such as a decal. Stencil may also be applied to produce stipples or screened door patterns which are sometimes employed to achieve transparency effect without resorting to the expensive multipliers and adders in the
Picking A computer graphics operation to select a drawn object on the display screen. A familiar example in 2D graphics is selecting an icon by clicking a mouse button. In 3D graphics, the selection is complicated by the Z values of objects and the size and locations (X, Y, Z) of the 3D selection cursor, and is supported by the on-chip Picking Logic. (Pages 12 and 55) Picking Logic A Pixel ALU function that provides to the rendering controller a HIT flag, indicating if a pixel falls within the 3D selection cursor. (Pages 12 and 55) Pixel ALU An on-chip 100-MHz (for the -10 speed grade) processing unit with a 7-stage pipeline that performs destination blending/logical raster operation, magnitude comparison, and match comparison all in parallel, thus converting the read-modify-write interface with the rendering controller to a write-mostly one. (Pages 9, 25 and 56) Pixel Buffer The triple-port 2,048-bit SRAM as a level-one pixel cache in 3D-RAM with two 100-MHz (for the -10 speed grade) 32-bit buses interfacing with the Pixel ALU and a 50-MHz (for the -10 speed grade) 256-bit bus interfacing with the DRAM arrays. Also included in the Pixel Buffer are eight 32-bit Dirty Tags and a 32-bit Plane Mask. (Pages 7 and 21) Plane Mask A 32-bit register that affects both the Stateful Data Writes to the Pixel Buffer and the Masked Block Writes (MBW) to the DRAM arrays. The effect is simultaneous on both types of operations when they are perfomed concurrently by the Pixel ALU port and the DRAM port, respectively. With respect to the Pixel Buffer, the Plane Mask facilitates the "write-per-bit" function on the 32-bit
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blending function. Stencil is also useful in hidden surface removal. (Pages 40 and 66) Video Buffer One of the two serial access video buffers of 40x16 bits, which alternates every forty VCLK cycles to shift video data out. One video buffer is connected with two DRAM banks, and all 640 bits of a video buffer are loaded by a single DRAM command (VDX). The video data output rate is 16 bits per 14-ns cycle. (Pages 7 and 78)
A unit of memory representing four bytes. This is the unit of data movement between the Pixel ALU and the Pixel Buffer. (Pages 4 and 21) Z Buffer The collection of memory that contains all Z values of all pixels to be displayed on the screen. (Pages 99 and 101)
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